1. Technical Field
The present invention relates generally to analog to digital converters and more particularly to a system and method for reducing power dissipation in analog to digital converters.
2. Discussion of Prior Art
Analog to Digital (A/D) converters serve to translate a given analog input signal (over a given range of potential signal values) into a corresponding digital signal. Some applications require the conversion accuracy to be very high while maintaining a high rate of conversion. For those applications requiring high conversion accuracy at a high conversion rate, more power is dissipated. This is problematic for applications, such as mobile applications, where power dissipation is of paramount importance. The increasing need for low power A/D conversion has fueled a trend towards ever-improving ADC power efficiency.
The prior art is replete with a host of different types of ADC architectures. They include, for example, flash architecture, pipelined architecture, successive approximation architecture and sigma delta architecture.
FIG. 1 illustrates a general block diagram 100 of a pipelined ADC of the prior art. This pipelined ADC divides an analog-to-digital conversion task into several consecutive stages, namely, a sample and hold stage 102, followed by one or more pipelined stages 104 106 and 108, and finally a flash stage 110.
The sample and hold stage 102 samples and holds the analog input signal. It is followed by a set of pipelined stages 104, 106, 108. Each pipelined stage produces a digital estimate of an analog held signal received at an input of the stage. More particularly, at each pipelined stage, a digital estimate of the analog held signal is performed, the digital estimate is then converted back to an analog waveform and is subtracted from the analog held signal received at the input of the stage. The result of the subtraction is referred to as residue. The residual analog signal is then amplified in the hold phase and supplied to the next stage in the pipeline 104, 106, 108 to be sampled and converted in an identical manner.
The last stage is a flash stage 110 that determines the Least Significant Bits (LSB). The successive digital results from the respective pipelined stages are appropriately delayed throughout a bit alignment network. Finally, a digital correction stage 112 helps to recover the errors due to the comparators offset.
Each of the pipelined stages 104, 106, 108, as shown in FIG. 1, is constructed in an identical manner. That is, each includes a sample and hold circuit 114, an ADC 116 (e.g. a flash converter), and a Digital to Analog (D/A) converter (DAC) 118. The ADC uses two clock phases, namely, a sample phase and a hold phase for A/D conversion. The sample phase is used to sample the input signal on the sampling caps (not shown). The input analog signal is the output voltage from the previous stage. For the hold phase, the input signal is the analog voltage which is supplied as an input to the ADC. The hold phase is used to calculate the residue. The sampled input analog signal is subtracted from the nearest DAC value determined by the comparator array. The subtracted output is commonly referred to as residue. These two phases are described in greater detail as follows.
Referring now to the sample phase of the sample and hold stage 102, the sample and hold circuit 114 acquires and samples the analog input signal. The ADC 116 then converts the sampled signal to digital data. The conversion result forms the Most Significant Bits (MSB) of the digital output. This same digital output is fed into the DAC 118, and its output is subtracted from the original sampled signal, the subtracted output is commonly referred to as residue. The residual analog signal is then amplified in the hold phase and supplied to the next stage in the pipeline to be sampled and converted in an identical manner to stage 1, 104. This process is repeated through as many stages as are necessary to achieve a desired resolution.
In conventional pipelined ADCs, the large load on the residue amplifier and small feedback factor in the ADC stages contribute to undesirable power consumption in ADCs. In conventional pipeline architectures as illustrated in FIG. 1, when any stage is in hold phase, the very next stage is in sample phase, or, when a stage is holding the residue value the very next stage is sampling the same residue value. Consequently, the 1st, 3rd, 5th etc. stages sample simultaneously and hold simultaneously; the 2nd, 4th, 6th etc. stages sample simultaneously and hold simultaneously. In accordance with the processes of sampling and holding, described above, both these factors namely, large load on the residue amplifier (load on the residue amplifier decides current) and small feedback factor in the circuit appears at the same time which in turn consumes a significant amount of power.
Hence, it would be advantageous to have a system and method for manipulating either of these two power consumption factors and thereby reduce the power dissipated in the ADC.
The present invention addresses these needs.